DDC - 1.0 English

The DDC I2C signals are implemented as bidirectional signals that use IOBUF in the FPGA. These signals can operate in either a 2.5V or 1.8V I/O bank. By definition in the standard, these are 3.3V signals.

For UltraScale+ devices supporting HP I/O banks, use the following constraints:

I/O Standard:

set_property IOSTANDARD LVCMOS18 [get_ports tx_ddc_out_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports tx_ddc_out_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports rx_ddc_out_sda_io] 
set_property IOSTANDARD LVCMOS18 [get_ports rx_ddc_out_scl_io] 

Sample Pin Assignments:

set_property PACKAGE_PIN A20 [get_ports tx_ddc_out_sda_io]
set_property PACKAGE_PIN B20 [get_ports tx_ddc_out_scl_io]
set_property PACKAGE_PIN A9 [get_ports rx_ddc_out_sda_io]
set_property PACKAGE_PIN B9 [get_ports rx_ddc_out_scl_io]

Board design and connectivity should follow HDMI Standard recommendations with proper level shifting.