In FRL mode, the CPLL dividers are configured to support 3, 6, 8, 10, and 12 Gb/s based on a single MGT reference clock frequency (400 MHz).
Note: For -1 speedgrade, the MGT reference
clock frequency is 200 Mhz.
| FRL Mode (Gb/s) | CPLL Ref Clk Divider | CPLL Multiplier | OUT_DIV | VCO Frequency |
|---|---|---|---|---|
| 3 | 1 | 15 | 4 | 6.0 |
| 6 | 1 | 15 | 2 | 6.0 |
| 8 | 1 | 10 | 1 | 4.0 |
| 10 | 2 | 25 | 1 | 5.0 |
| 12 | 1 | 15 | 1 | 6.0 |