In FRL mode, the QPLL0 dividers are configured to support 3, 6, 8, 10, and 12 Gb/s based on a single MGT reference clock frequency (400 MHz).
Note: For -1 speedgrade, the MGT reference
clock frequency is 200 Mhz.
| FRL Mode (Gb/s) | QPLL0 Ref Clk Divider | QPLL0 Multiplier | OUT_DIV | VCO Frequency |
|---|---|---|---|---|
| 3 | 2 | 60 | 4 | 12.0 |
| 6 | 2 | 60 | 2 | 12.0 |
| 8 | 1 | 40 | 2 | 16.0 |
| 10 | 3 | 75 | 1 | 10.0 |
| 12 | 2 | 60 | 1 | 12.0 |
Note: The GTHE4 and GTYE4
RX' PPM tolerance at 12.0 Gb/s and 10.0 Gb/s is 200 PPM. It is recommended to use a retimer
device to ensure proper operation.