Fourth GT Channel Usage in TMDS Mode and FRL Mode - 1.0 English

The fourth GT Channel is used as TX TMDS clock in TMDS Mode.

A pattern generator module is added in the HDMI PHY Controller architecture to generate the specific pattern needed to generate the required TMDS clock frequency from the fourth GT channel. The pattern generator control register is located at offset 0x340 and is programmed based on the line rate to TMDS clock ratio. The pattern generator supports ratios of 10, 20, 30, 40, and 50. For example, in a typical HDMI 1.4 resolution such as 1080p60, the line rate per channel is 1.485 Gb/s and the TMDS clock is 148.5 MHz, thus giving a ratio of 10. For low line rate resolutions such as 480P60 which needs an oversampling technique (for example, x3) to be transmitted, the ratio is computed as the actual line rate per channel (270 Mb/s x 3) over TMDS clock (27 MHz), which gives a ratio of 30. For HDMI 2.0 resolution such as 4KP60, the line rate is 5.94 Gb/s and the TMDS clock is 148.5 MHz, thus giving a ratio of 40.

In FRL mode, the fourth GT channel is used to transmit FRL data. Multiplexing between TMDS clock pattern and FRL data is automatically and internally handled by the HDMI PHY Controller and its software driver, depending on the operating mode.