The following parameters affect the clocking of the GTHE4 and GTYE4 device.
- Adv_Clk_Mode
- Configured through a check box in the Vivado IDE.
This controls where the IBUFDS_GTE4 clock buffers of MGTREFCLK0 and MGTREFCLK1 are placed. When disabled, IBUFDS_GTE4 is placed within the HDMI PHY Controller. When enabled, IBUFDS_GTE4 should be manually instantiated at the system level. This is an ideal mode for applications requiring reference clock sharing across multiple HDMI PHY Controller instances.
- C_Rx_Tmds_Clk_Buffer
- Configured through a Tcl command or through the Block Properties window in
IP integrator. This controls the type of
buffer to be used for driving the fabric associated with the RX TDMS output
clock.
Valid parameters are: none, bufg, bufh, bufmr, and bufr.
- C_Tx_Tmds_Clk_Buffer
- Configured through a Tcl command or through the Block Properties window in
IP integrator. This controls the type of
buffer to be used for driving the fabric associated with theTX TMDS output
clock.
Valid parameters are: none, bufg, bufh, bufmr, and bufr.
- C_Tx_Video_Clk_Buffer
- Configured through a Tcl command or through the Block Properties
window in IP integrator. This controls the
type of buffer to be used for driving the fabric associated with theTX Video
output clock.
Valid parameters are: none, bufg, bufh, bufmr, and bufr.
- C_Rx_Video_Clk_Buffer
- Configured through a Tcl command or through the Block Properties
window in IP integrator. This controls the
type of buffer to be used for driving the fabric associated with theRX Video
output clock.
Valid parameters are: none, bufg, bufh, bufmr, and bufr.
- C_Use_Oddr_for_Tmds_Clkout
- Configured through a Tcl command or through the Block Properties
window in IP integrator. This controls
whether an ODDRE1 is inserted to drive the OBUFTDS for differential TX and RX
TMDS output clocks.
Valid parameters are: TRUE or FALSE.