The HDMI PHY Controller IP generates the TX TMDS, link, and video clocks that the HDMI 2.1 Transmitter Subsystem requires. See the Clocking section of the HDMI 2.1 Transmitter Subsystem Product Guide (PG350) for more information.
The HDMI PHY Controller IP generates the RX link and video clocks that the HDMI 2.1 Receiver Subsystem requires. See the Clocking section of the HDMI 2.1 Receiver Subsystem Product Guide (PG351) for more information.