The frequency range of the external programmable clock generator must be selected based on the transceiver type and the PLL type for TX. The following table shows the frequency range needed from the clock generator if the HDMI PHY Controller is used to support all the video formats in the tables in the HDMI PHY Controller HDMI Implementation section.
Configuration | TX PLL | Reference Clock Range (MHz) |
---|---|---|
GTHE4/GTYE4 | CPLL | 50 to 297 |
QPLL0 | 61.25 to 297 |
The following table shows the external clock generator frequency range if the HDMI PHY Controller TX is used to support video formats of SMPTE-SDI: SD-SDI, HD-SDI, and 3G-SDI which in HDMI have equivalent TMDS clocks 27, 74.25, or 74.25/1.001 MHz and 148.5 or 148.5/1.001 MHz, respectively. SD-SDI reference clock is below the minimum threshold of all PLL types thus oversampling mode must be used to support it. HD-SDI reference clock is below the minimum threshold of the GTHE4 CPLL, thus oversampling mode must be used to support it for the corresponding GT and PLL types.
Transceiver Type | TX PLL | Reference Clock Range (MHz) | Remarks |
---|---|---|---|
GTHE4/GTYE4 | CPLL | 135 to 222.75 |
SD-SDI uses x5 oversampling HD-SDI uses x3 oversampling |
QPLL0 | 74.25/1.001 to 148.5 | SD-SDI uses x3 oversampling |