High-Speed I/O - 1.0 English

HDMI PHY Controller LogiCORE IP Product Guide (PG333)

Document ID
PG333
Release Date
2023-12-01
Version
1.0 English

The three or four differential pairs of TX and RX high-speed lanes are implemented as GT TX and RX channels, respectively. Therefore, I/O standard constraints are not required. Board design and connectivity should follow HDMI standard recommendations.

For UltraScale+ devices, actual pin assignments are absorbed by the GT Wizard instance in the HDMI PHY Controller. Therefore, pin assignment constraints are not required.