| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 | AMD UltraScale+™ families (GTHE4, GTYE4) |
| Supported User Interfaces | AXI4-Stream, AXI4-Lite |
| Resources |
HDMI PHY web page (registration required). |
| Provided with Core | |
| Design Files | Verilog |
| Example Design | Provided with the HDMI IP subsystems. 3 |
| Test Bench | Not Provided |
| Constraints File | AMD Design Constraints (XDC) |
| Simulation Model | Not Provided |
| Supported S/W Driver 3 | Standalone |
| Tested Design Flows 4 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 72241 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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