Valid interrupt event by AND of IMR and ISR.
| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 0 | 0 | W1C | TX Reset Done Change Event: Triggers an interrupt whenever the state of reset done changes. SW has to read the TXIS register to know reset done state. |
| 1 | 0 | W1C | RX Reset Done Change Event Triggers an interrupt whenever the state of reset done changes. SW has to read the RXIS register to know reset done state. |
| 2 | 0 | W1C | CPLL Lock Change Event Triggers an interrupt whenever the state of CPLL Lock changes. SW has to read the PLS register to know lock state. |
| 3 | 0 | W1C | QPLL/QPLL0 Lock Change Event
Triggers an interrupt whenever the state of QPLL Lock changes. SW has to read the PLS register to know lock state. |
| 4 | 0 | W1C | TX Alignment Done Event |
| 5 | 0 | W1C | QPLL1 Lock Change Event
Triggers an interrupt whenever the state of QPLL1 Lock changes. SW has to read the PLS register to know lock state. |
| 6 | 0 | W1C | Clock Detector TX Frequency Change |
| 7 | 0 | W1C | Clock Detector RX Frequency Change |
| 9 | 0 | W1C | TX MMCM Lock Change Event |
| 10 | 0 | W1C | RX MMCM Lock Change Event |
| 30 | 0 | W1C | Clock Detector TX Debounce Timeout |
| 31 | 0 | W1C | Clock Detector RX Debounce Timeout |