Clock override critical warnings on TXOUTCLK or RXOUTCLK GT pins
when compiling the HDMI PHY Controller are known issues and can
be ignored. This is necessary for constraining the GT pins per target maximum line rate.
This is not normally a recommended flow but has been done for this specific case. The
following is an example of the critical warning:
[Constraints 18-1056] Clock '<HDMIPHY Path>/gtxe2_i/TXOUTCLK' completely overrides clock '<HDMIPHY Path>/gtxe2_i/TXOUTCLK'.New:
create_clock -period 3.704 [get_pins [list <HDMIPHY Path>/gtxe2_i/TXOUTCLK <HDMIPHY Path>/gtxe2_i/TXOUTCLK <HDMIPHY Path>/gtxe2_i/TXOUTCLK <HDMIPHY Path>/gtxe2_i/TXOUTCLK]], ["<Project Path>/project_1.srcs/sources_1/bd/design_1/ip/design_1_v_hdmi_phy_0_0/v_hdmi_phy_xdc.xdc": and 43]Previous:
create_clock -period 24.692 [get_pins <HDMIPHY Path>/gtxe2_i/TXOUTCLK], ["<Project Path>/project_1.srcs/sources_1/bd/design_1/ip/design_1_v_hdmi_phy_0_0/ip_0/design_1_v_hdmi_phy_0_0_gtwrapper.xdc": and 83]Note: TIMING-17
is by design and can be ignored. The following is an example of a critical
warning.
TIMING-17#1 Critical Warning
Non-clocked sequential cell
The clock pin DUT/inst/tx_tmdsclk_patgen_inst/txdata_counter_reg[0]/C is not reached by a timing clock