Table 1. Power Down Control (PDC) Register
| Bit |
Default Value |
Access Type |
Description |
| Channel 1 |
| 0 |
N/A
|
N/A
|
Reserved
|
| 1 |
0 |
RW |
QPLL0PD
|
| 2 |
0 |
RW |
QPLL1PD
|
| 4:3 |
0 |
RW |
RXPD[1:0] |
| 6:5 |
0 |
RW |
TXPD[1:0] |
| 7 |
N/A |
N/A |
Reserved |
| Channel 2 |
| 8 |
N/A
|
N/A
|
Reserved
|
| 10:9 |
N/A |
N/A |
Reserved |
| 12:11 |
0 |
RW |
RXPD[1:0] |
| 14:13 |
0 |
RW |
TXPD[1:0] |
| 15 |
N/A |
N/A |
Reserved |
| Channel 3 |
| 16 |
N/A
|
N/A
|
Reserved
|
| 18:17 |
N/A |
N/A |
Reserved |
| 20:19 |
0 |
RW |
RXPD[1:0] |
| 22:21 |
0 |
RW |
TXPD[1:0] |
| 23 |
N/A |
N/A |
Reserved |
| Channel 4 |
| 24 |
N/A
|
N/A
|
Reserved
|
| 26:25 |
N/A |
N/A |
Reserved |
| 28:27 |
0 |
RW |
RXPD[1:0] |
| 30:29 |
0 |
RW |
TXPD[1:0] |
| 31 |
N/A |
N/A |
Reserved |