RX Equalization and CDR Register (0x0108) - 1.0 English

HDMI PHY Controller LogiCORE IP Product Guide (PG333)
Document ID
PG333
Release Date
2023-12-01
Version
1.0 English
Table 1. RX Equalization and CDR Register
Bit Default Value Access Type Description
Channel 1
0 0 RW RXLPMEN
1 0 RW RXCDRHOLD
2 0 RW RXOSOVRDEN
3 0 RW RXLPMLFKLOVRDEN
4 0 RW RXLPMHFOVRDEN
5:7 0 RW Reserved
Channel 2
8 0 RW RXLPMEN
9 0 RW RXCDRHOLD
10 0 RW RXOSOVRDEN
11 0 RW RXLPMLFKLOVRDEN
12 0 RW RXLPMHFOVRDEN
15:13 0 RW Reserved
Channel 3
16 0 RW RXLPMEN
17 0 RW RXCDRHOLD
18 0 RW RXOSOVRDEN
19 0 RW RXLPMLFKLOVRDEN
20 0 RW RXLPMHFOVRDEN
23:21 0 RW Reserved
Channel 4
24 0 RW RXLPMEN
25 0 RW RXCDRHOLD
26 0 RW RXOSOVRDEN
27 0 RW RXLPMLFKLOVRDEN
28 0 RW RXLPMHFOVRDEN
31:29 0 RW Reserved