Reference Clock Selection (RCS) Register (0x0010) - 1.0 English

HDMI PHY Controller LogiCORE IP Product Guide (PG333)
Document ID
PG333
Release Date
2023-12-01
Version
1.0 English
Table 1. Reference Clock Selection Register
Bit Default Value Access Type Description
3:0 0 RW QPLL0REFCLKSEL
7:4 0 RW CPLLREFCLKSEL
11:8 0 RW QPLL1REFCLKSEL
23:12 0 RW Reserved
27:24 0 RW {TXSYSCLKSEL[1:0], RXSYSCLKSEL[1:0]}
31:28 0 RW {TXPLLCLKSEL[1:0], RXPLLCLKSEL[1:0]}