Because the largest multiplier that can be applied by the CPLL is 40, the minimum TMDS clock frequency that the CPLL can support is 50 MHz. Video formats that have a TMDS clock frequency of less than 50 MHz are not supported by the CPLL.
When the GT driver detects that the TMDS clock frequency is less than 50 MHz, it enables the NI-DRU to receive these low bit rates that are less than 500 Mb/s. The NI-DRU runs at 2.5 Gb/s, which enables it to recover line rates that the CPLL cannot support.
For TMDS clock frequencies greater than 50 MHz, a multiplier of 10X, 20X, or 40X is applied to keep the VCO frequency in the proper range as shown in the following table.
TMDS Clock Frequency (MHz) | CPLL Refclk Divider | CPLL Multiplier | VCO Frequency | Notes |
---|---|---|---|---|
<50 |
TX: Line Rate Dependent RX: 2 |
TX: Line Rate Dependent RX: 16 |
TX: Line Rate Dependent RX: 2.5 GHz |
TX: Oversampling RX: NI-DRU is used |
50 to 156.25 | 1 | 40 |
2.0 to 6.25 GHz |
CDR is used |
100 to 312.5 | 1 | 20 |
2.0 to 6.25 GHz |
CDR is used |
312.5 to 340 | 1 | 10 | 3.125 to 3.4 GHz | CDR is used |
The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.
Resolution (Hz) | Bits Per Pixel | |||
---|---|---|---|---|
24 | 30 | 36 | 48 | |
480i60 | DRU | DRU | DRU | √ |
576i50 | DRU | DRU | DRU | √ |
1080i50 | √ | √ | √ | √ |
1080i60 | √ | √ | √ | √ |
480p60 | DRU | DRU | DRU | √ |
576p50 | DRU | DRU | DRU | √ |
720p50 | √ | √ | √ | √ |
720p60 | √ | √ | √ | √ |
1080p24 | √ | √ | √ | √ |
1080p25 | √ | √ | √ | √ |
1080p30 | √ | √ | √ | √ |
1080p50 | √ | √ | √ | √ |
1080p60 | √ | √ | √ | √ |
2160p24 | √ | √ | √ | √ |
2160p25 | √ | √ | √ | √ |
2160p30 | √ | √ | √ | √ |
2160p60 | √ | (1) | (1) | (1) |
VGA 60 | DRU | DRU | DRU 3 | √ 3 |
SVGA 60 | DRU | DRU | √ | √ |
XGA 60 | √ | √ | √ | √ |
SXGA 60 | √ | √ | √ | √ |
WXGA 60 | √ | √ | √ | √ |
WXGA + 60 | √ | √ | √ | √ |
UXGA 60 | √ | √ | √ | √ |
WUXGA 60 | √ | √ | √ | √ |
WSXGA 60 | √ | √ | √ | √ |
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