TX Buffer Bypass Control (TXBBC) Register (0x0074) - 1.0 English

HDMI PHY Controller LogiCORE IP Product Guide (PG333)
Document ID
PG333
Release Date
2023-12-01
Version
1.0 English
Table 1. TX Buffer Bypass Control Register
Bit Default Value Access Type Description
Channel 1
0 0 RW TXPHDLYRESET
1 0 RW TXPHALIGN
2 0 RW TXPHALIGNEN
3 0 RW TXPHDLYPD
4 0 RW TXPHINIT
5 0 RW TXDLYRESET
6 0 RW TXDLYBYPASS
7 0 RW TXDLYEN
Channel 2
8 0 RW TXPHDLYRESET
9 0 RW TXPHALIGN
10 0 RW TXPHALIGNEN
11 0 RW TXPHDLYPD
12 0 RW TXPHINIT
13 0 RW TXDLYRESET
14 0 RW TXDLYBYPASS
15 0 RW TXDLYEN
Channel 3
16 0 RW TXPHDLYRESET
17 0 RW TXPHALIGN
18 0 RW TXPHALIGNEN
19 0 RW TXPHDLYPD
20 0 RW TXPHINIT
21 0 RW TXDLYRESET
22 0 RW TXDLYBYPASS
23 0 RW TXDLYEN
Channel 4
24 0 RW TXPHDLYRESET
25 0 RW TXPHALIGN
26 0 RW TXPHALIGNEN
27 0 RW TXPHDLYPD
28 0 RW TXPHINIT
29 0 RW TXDLYRESET
30 0 RW TXDLYBYPASS
31 0 RW TXDLYEN