TX TMDS Pattern Generator Control Register (0x0340) - 1.0 English

HDMI PHY Controller LogiCORE IP Product Guide (PG333)

Document ID
PG333
Release Date
2023-12-01
Version
1.0 English
Table 1. TX TMDS Pattern Generator Control Register
Bit Default Value Access Type Description
2:0 0 RW Clock Ratio
  • 0x0 - OFF
  • 0x1 - Ratio - 10
  • 0x2 - Ratio - 20
  • 0x3 - Ratio - 30
  • 0x4 - Ratio - 40
  • 0x5 - Ratio - 50
  • 0x6 - OFF
  • 0x7 - OFF
31 0 RW Enable:
  • 1: Enable
  • 0: Disable
Note: When the PLL clock primitive is selected, the same registers and register bits used for configuration are the same as when the MMCM clock primitive is selected.