User Parameters - 1.0 English

HDMI PHY Controller LogiCORE IP Product Guide (PG333)

Document ID
PG333
Release Date
2023-12-01
Version
1.0 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Vivado IDE Parameter/Value User Parameter/Value Default Value Register Encoding
TX/RX Protocol Selection C_Tx/Rx_Protocol HDMI 2.1
  • HDMI 2.1
     
  • None
     
TX/RX Clock Primitive C_Tx/Rx_Clk_Primitive MMCM  
TX/RX Max GT Line Rate Tx/Rx_Max_GT_Line_Rate

6.0 Gb/s, 12.0 Gb/s

TX/RX Clock Primitive C_Tx/Rx_Clk_Primitive MMCM  
TX/RX Channels C_Tx/Rx_No_Of_Channels

3, 4

Tx PLL Type 1 C_TX_PLL_SELECTION

6

TX/RXSYSCLKSEL

TX/RXPLLCLKSEL

  • CPLL: 0
  00
  • QPLL0/1: 6
  Follow QPLL0 or QPLL1 encoding
Rx PLL Type 1 C_RX_PLL_SELECTION 0 Similar to TX PLL Type
Tx Ref Clock Selection 1 C_TX_REFCLK_SEL 1
  • GTREFCLK0: 0
  • GTREFCLK1: 1
  • GTNORTHREFCLK0: 2
  • GTNORTHREFCLK1: 3
  • GTSOUTHREFCLK0: 4
  • GTSOUTHREFCLK1: 5
 
  • 001
  • 010
  • 011
  • 100
  • 101
  • 110
Tx FRL Ref Clock Selection C_TX_FRL_REFCLK_SEL 2  
Rx Ref Clock Selection 1 C_RX_REFCLK_SEL 0 Similar to Tx Ref Clock Selection
Rx FRL Ref Clock Selection C_RX_FRL_REFCLK_SEL 2
Tx Buffer Bypass Tx_Buffer_Bypass

True

TX REFCLK Ready Active C_Txrefclk_Rdy_Invert High
NI-DRU C_NIDRU TRUE
NI-DRU Ref Clock Selection C_NIDRU_REFCLK_SEL 2 Similar to Tx Ref Clock Selection
Advanced Clock Mode Adv_Clk_Mode false
Number of pixels per clock Value Selection
  • 4
C_INPUT_PIXELS_PER_CLOCK 4
DRP Clock Frequency (MHz) DRPCLK_FREQ

100

Insertion Loss at Nyquist (dB) C_user_loss 20  
Transceiver Width Value Selection
  • 4
Transceiver_Width 4
GT: Starting channel Location CHANNEL_SITE the lowest number from available X<num>Y<num> in GT
Use ODDR/ODDRE1 for TX and RX differential TMDS clock out C_Use_Oddr_for_Tmds_Clkout 3 TRUE
TX TMDS Clock output buffer

none, bufg 4

C_Tx_Tmds_Clk_Buffer 3

bufg

TX Video Clock output buffer

none, bufg 4

C_Tx_Video_Clk_Buffer 3 bufg
RX TMDS Clock output buffer

none, bufg 4

C_Rx_Tmds_Clk_Buffer 3 bufg
RX Video Clock output buffer

none, bufg 4

C_Rx_Video_Clk_Buffer 3 bufg

TX Phase Interpolator port enable

C_TXPI_Port_EN 1 none
  1. The Vivado IDE Parameter/Values are only used for the HDMI PHY Controller IP configuration in the Vivado IDE and are not the actual register encoding used to configure the Reference Clock Selection Register at offset 0x0010. The HDMI PHY Controller driver converts these parameters to the corresponding register encoding in the Register Encoding column.
  2. The Vivado IDE Parameter/Values are only used for the HDMI PHY Controller IP configuration in Vivado environment and are not the actual register encoding used to configure the PLL REFCLKSEL bits (11:0) of the Reference Clock Selection Register at offset 0x0010. The HDMI PHY Controller driver converts these parameters to the corresponding register encoding in the Register Encoding column.
  3. The user parameter applies to HDMI only and can be configured through Tcl command or through the Block Properties Window in IP integrator. Example:
    set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {none}] [get_ips <ip name>] 
    set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip name>] 
    set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}] [get_ips <ip name>] 
    set_property -dict [list CONFIG.C_TXPI_Port_EN {true}] [get_ips <ip name>]
  4. See Clocking.