HDMI GT Controller LogiCORE IP Product Guide (PG334) - 1.0 English

Document ID: PG334
Release Date: 2022-04-21
Version: 1.0 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Applications
Unsupported Features
Licensing and Ordering
License Checkers
Product Specification
Performance
Resource Use
Port Descriptions
Clock, Reset, and Initialization Ports
GT Interface Ports
HDMI Interface Ports
Sideband Signal Ports (Optional)
HDMI Transmit - Status Path
HDMI Receive - Status Path
AXI4-Lite Ports
Register Space
Version Register (0x0000)
Reset Register (PR) (0x0014)
PLL Lock Status (PLS) Register (0x0018)
TX Initialization (TXI) Register (0x001C)
TX Initialization Status (TXIS) Register (0x0020)
RX Initialization (RXI) Register (0x0024)
RX Initialization Status (RXIS) Register (0x0028)
GT_DBG_CONTROL (GTDBGC) (0x0068)
GT_DBG_STATUS (GTDBGS) (0x006C)
TX Status (TXS) Register (0x0078)
TX Channel Control – Channel 1 and 2 Register (0x007C)
TX Channel Control – Channel 3 and 4 Register (0x0080)
TX Channel Control Channel 1 to 4 Register (0x0084)
TX DRIVER Control Extension Channel 1 and 2 Register (0x008C)
TX DRIVER Control Extension Channel 3 and 4 Register (0x0090)
RX DRIVER Control Extension Channel 1 and 2 Register (0x0098)
RX DRIVER Control Extension Channel 3 and 4 Register (0x009C)
RX Status (RXS) Register (0x0104)
RX Equalization and CDR Register (0x0108)
Interrupt Enable Register (IER) (0x0110)
Interrupt Disable Register (IDR) (0x0114)
Interrupt Mask Register (IMR) (0x0118)
Interrupt Status Register (ISR) (0x011C)
MMCM TXUSRCLK Control/Status (MMCM_TXUSRCLK_CTRL) Register (0x0120)
DRP CONTROL MMCM TXUSRCLK Register (0x0124)
DRP STATUS MMCM TXUSRCLK Register (0x0128)
MMCM RXUSRCLK Control/Status (MMCM_RXUSRCLK_CTRL) Register (0x0140)
DRP CONTROL MMCM RXUSRCLK Register (0x0144)
DRP STATUS MMCM RXUSRCLK Register (0x0148)
Clock Detector Control Register (0x0200)
Clock Detector Status Register (0x0204)
Clock Detector Frequency Counter Timeout Register (0x0208)
Clock Detector Transmitter Frequency Register (0x020C)
Clock Detector Receiver Frequency Register (0x0210)
Clock Detector Transmitter Timer Register (0x0214)
Clock Detector Receiver Timer Register (0x0218)
Clock Detector DRU Frequency Register (0x021C)
Data Recovery Unit Control Register (0x0300)
Data Recovery Unit Status Register (0x0304)
Data Recovery Unit Center Frequency Low Register – All Channels Register (0x0308)
Data Recovery Unit Center Frequency High Register – All Channels Register (0x030C)
Data Recovery Unit Gain Register – All Channels (0x0310)
TX TMDS Pattern Generator Control Register (0x0340)
Designing with the Core
Clocking
Connecting GT Reference Clocks to HDMI GT Controller and GT Wizard
Using 4th GT Channel as the TX TMDS Clock Source
Resets
Interrupts
Program and Interrupt Flow
HDMI TX Flow
HDMI GT Controller Core Driver TX Callbacks
HDMI RX Flow
HDMI GT Controller Core Driver RX Callbacks
Versal ACAP GTY HDMI GT Controller Implementation
TMDS Mode RPLL Use
FRL Mode RPLL Use
TMDS Mode LCPLL Use
FRL Mode LCPLL Use
Design Flow Steps
Customizing and Generating the Core
Configuration Tab
User Parameters
Output Generation
Constraining the Core
Out-of-Context Constraints
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Reference Clock Requirements
HDMI TX Oversampled Reference Clock Requirements
HDMI TX Clock Requirement Example
HDMI Generated Clocks
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
TMDS Clock
High-Speed I/O
Board Design Guidelines - HDMI
Synthesis and Implementation
Example Design
Verification, Compliance, and Interoperability
Upgrading
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
HDMI Debugging
TX Only Sample HDMI GT Controller Log
RX Only Sample HDMI GT Controller Log
Passthrough Sample HDMI GT Controller Log
Application Software Development
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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