Clocking - 1.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID
PG334
Release Date
2022-04-21
Version
1.0 English

The HDMI GT Controller clocking diagrams per transceiver type are shown as follows. Use the following guidelines when connecting the HDMI GT Controller clock ports or refer to the example design.

  • Connect the external clock generator output clock to the TX reference clock input that was selected in the HDMI GT Controller Vivado® IDE. The TX reference clock lock indicator should be connected to the tx_refclk_rdy port. See HDMI Reference Clock Requirements (link below) for its implementation.
  • Connect the RX TMDS clock from the external HDMI retimer component clock output to the corresponding RX reference clock input that was selected in the HDMI GT Controller IDE.
  • Connect the DRU and FRL mode reference clock to the reference clock input that was selected in the HDMI GT Controller IDE. See HDMI Reference Clock Requirement for the NI-DRU and FRL mode frequency requirements.
  • The gt_txusrclk/gt_rxusrclk signal is connected to the HDMI MAC controller and the chN_txusrclk/chN_rxusrclk ports of the GT Wizard.
  • The tx_video_clk/rx_video_clk signals are connected to the HDMI MAC controller.
  • The tx_tmds_clk_p/n signal should be connected to the HDMI TX connector.
  • The tx_tmds_clk signal can be connected to any logic, for example, audio generator module.
  • The rx_tmds_clk_p/n signal should be connected to the input of the external clock generator if the HDMI GT Controller is used in pass through mode. This is to have a phase aligned and jitter attenuated reference clock for the HDMI TX Subsystem.
  • The rx_tmds_clk signal can be connected to any logic.
  • The gt_refclk[0-5]_odiv2 signal is connected to the respective bufg_gt output. This is the refclk that can be used in PL.
  • The rx_axi4s_aclk and tx_axi4s_aclk signals should be connected to the streaming clock similar to the gt_rxusrclk/gt_txusrclk signal.
  • The sb_clk, axi4lite_aclk and apb_clk signals can all be same.
  • The gt_lcpll0/1_lock and gt_rpll0/1_lock signals should be connected to the respective lock output signal of the GT quad.
Note: The HDMI RX and TX Subsystem clocks must be phase aligned in pass through mode to ensure seamless video streaming. Otherwise, the video output intermittently breaks due to mismatching clocks. This connection is not needed if the HDMI GT Controller is used in a TX-only application because the external clock generator should run in standalone mode, using its local oscillator as its reference.

The following clocking diagrams show the default clock buffers. These buffers can be changed by users according to their own application, through the user configurable parameters. These parameters are in white dash-lined boxes with prefix CONFIG.<user_param_name>.

Important: The HDMI GT Controller has been tested using the default settings. You are expected to understand the proper clock buffer usage and design implications when changing the user parameters. See the Versal ACAP Clocking Resources Architecture Manual (AM003).

The user parameters can be configured using Tcl commands or through the Block Properties window in IP integrator. For example:

set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}] [get_ips <ip name>]
set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {none}] [get_ips <ip name>]
set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip name>]
Figure 1. HDMI GT Controller Clocking Diagram