Core Overview - 1.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID
PG334
Release Date
2023-10-18
Version
1.0 English

The HDMI GT Controller core is a feature-rich soft IP core that incorporates all the necessary logic to properly interface with media access control (MAC) layers and controls the physical-side interface (PHY) functionality. AMD IP cores are tested on hardware and verified successfully. For additional details on the interoperability results, contact your local Xilinx sales representative.

The core is intended to simplify the use of serial transceivers and adds domain-specific configurability. The HDMI GT Controller IP is not intended to be used as a standalone IP and must be used with AMD Video MACs such as the HDMI™ 1.4/2.0/2.1 Transmitter/Receiver Subsystems. The core enables simpler connectivity between MAC layers for TX and RX paths, and PHY layers. However, it is still important to understand the behavior, use, and limitations of the transceivers. See the device-specific transceiver user guide for details.

The following figure shows the standard OSI Model and mapping it with video IP solutions.

Figure 1. OSI Mapping of Video Systems

In accordance with the OSI model, the major PHY component for video IP cores is SerDes. Standardizing the SerDes delivery model provides benefits and flexibility for a video MAC layer at the system level.

The following figure shows the boundary between these MAC and PHY layers and the key highlights are:

  • AXI4-Lite interface to provide software access.
  • AXI4-Stream-based interface for easier connectivity between different video link layers.
  • GT TX Interface: Standard GT TX channel interface for simpler connectivity (input and output ports) between Parent IP and GT Wizard. On top of IO connectivity, the interface also carries the TX side configuration information of the GT Wizard such as the Line Rate Table. The GT is also referred to as a serial transceiver.
  • GT RX Interface: Standard GT RX channel interface for simpler connectivity (input and output ports) between Parent IP and GT Wizard. On top of IO connectivity, the interface also carries the RX side configuration information of the GT Wizard such as the Line Rate Table.
Figure 2. Video IP Layer