In TMDS mode, a change in the TX reference clock signifies a video format
change which triggers a series of interrupts until the GT TX attains the TX Reset Done
status. The TX frequency change is based on the toggling (deassertion then assertion) of
tx_refclk_rdy port or it can be forced by setting
TX Frequency Reset bit (bit 3) of the Clock Detector Control register (0x200). This bit
is self clearing. See HDMI Reference Clock Requirements (link below) for details about
tx_refclk_rdy port implementation.
There are several API callback hooks that the HDMI GT Controller core execute throughout the HDMI TX operation. If necessary, these callbacks are available for inserting or adding more function calls on top of what is in the software application.
TX FRL mode is entered when the
XHdmiphy1_Hdmi21Config API is called in the application. It requires the
target FRL rate (3, 6, 8, 10, and 12 Gb/s) and number of channels (3 or 4). After which,
it performs all tasks under the TX Timer Timeout Intr to eventually attain TX Alignment