In normal cases, the GT reference clock requirement is equal to the TMDS clock requirement of a given HDMI resolution.
HdmiTxRefClkHzvariable in the HDMI GT Controller data structure declared in the application (for example, in reference design:
HdmiTxRefClkHzvalue is valid and can be accessed any time after TX Timer Timeout Interrupt occurs (see the HDMI TX Flow). This value is ideally used in programming the external clock generator frequencies for GT TX operation.
The HDMI GT Controller TX application enters the oversampling mode when the reference clock and line rate required by video resolution to be transmitted is below the minimum supported by the transceiver. The HDMI GT Controller driver increases the reference clock and line rate by a factor of x2, x3, or x5 until the minimum line rate for the transceiver is achieved. The following table shows the minimum line rate per transceiver and PLL type.
For example, the GTYE5 and GTYP LCPLL need to transmit 480p 60 Hz at eight bits per component. This video format requires a TMDS clock and line rate of 27 MHz and 270 Mbps, respectively, which is below the GTYE5 and GTYP's minimum supported line rate. The HDMI GT Controller driver searches for the oversampling factor that satisfies this condition, which is x5. The new GT reference clock and line rate are 135 MHz and 1.35 Gbps.
|Transceiver Type||PLL Type||Min Reference Clock/Line Rate (MHz)|
|GTYE5 and GTYP||LCPLL||125 MHz / 1.25 Gbps|
|RPLL||125 MHz / 1.25 Gbps|