Core Specifics |
Supported Device Family
|
Versal®
ACAP GTYE5 Transceivers |
Supported User Interfaces |
AXI4-Stream, AXI4-Lite
|
Resources |
Performance and Resource Use web
page
|
Provided with
Core
|
Design Files |
Verilog |
Example Design |
Provided with the HDMI IP subsystems
|
Test Bench |
Not Provided |
Constraints File |
Xilinx Design Constraints (XDC) |
Simulation Model |
Not Provided |
Supported S/W Driver
|
Standalone |
Tested Design
Flows
3
|
Design Entry |
Vivado® Design Suite
|
Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Record: 72991
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Xilinx
Support web page
|
- For a complete list of
supported devices, see the
Vivado®
IP
catalog.
-
Standalone driver details can be found in <Install
Directory>/Vitis/<Release>/data/embeddedsw/doc/Xilinx_drivers.htm.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
|