Interrupt Status Register (ISR) (0x011C) - 1.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID
PG334
Release Date
2023-10-18
Version
1.0 English

Valid interrupt event by AND of IMR and ISR.

Table 1. Interrupt Status Register
Bit Default Value Access Type Description
0 0 W1C TX Reset Done Change Event:

Triggers an interrupt whenever the state of reset done changes. SW has to read the TXIS register to know reset done state.

1 0 W1C RX Reset Done Change Event

Triggers an interrupt whenever the state of reset done changes. The software has to read the RXIS register to find out the reset done state.

3 0 W1C LCPLL Lock Change Event

Triggers an interrupt whenever the state of LCPLL Lock changes. The software has to read the PLS register to find out the lock state.

5 0 W1C RPLL Lock Change Event

Triggers an interrupt whenever the state of RPLL Lock changes. The software has to read the PLS register to find out the lock state.

6 0 W1C Clock Detector TX Frequency Change
7 0 W1C Clock Detector RX Frequency Change
9 0 W1C TX MMCM Lock Change Event
10 0 W1C RX MMCM Lock Change Event
11 0 W1C TX GPO Change Event
12 0 W1C RX GPO Change Event
30 0 W1C Clock Detector TX Debounce Timeout
31 0 W1C Clock Detector RX Debounce Timeout