The HDMI GT Controller core is the supported method of configuring and using transceivers with MAC subsystems. The core simplifies serial transceiver (GT) use by providing a standardized interface and software programmability of serial transceiver functions. The standardized GT interface carries the GT Wizard configuration information based on the HDMI GT Controller configuration which are passed to the GT Wizard when Block Automation is executed in the IP integrator canvas.
The functional block diagram of the core is shown in the following figure.
- AXI4-Lite Control/Status Manager
- This block manages AXI4-Lite bus protocol accesses and handles memory map accesses and interrupt management.
- Clock Detector
- This block contains frequency counters to determine the corresponding GT operation based on the incoming GT reference clock frequency.
- GT Reset Controller
- This block contains GT Reset IPs specially made to assist in the Versal GT initialization.
- This block is used in applications where lower line rates (those below
the rates supported by the respective GTs) are needed. In
, the NI-DRU is enabled when the RX TMDS clock is below the threshold
of the specific GT type.
- GTYE5 Thresholds
- LCPLL = 125.000 MHz
- RPLL = 125.0 MHz
The NI-DRU requires an additional fixed reference clock to the GT RX (as well as the RX TMDS clock) to run the low line rate data recovery. For more information on the reference clock frequency requirement per transceiver type, see Reference Clock Requirements (link below).
- GTYE5 Thresholds
- Control and Status Mapper
- This block maps the AXI4-Lite control and status registers to the corresponding GT ports within the GT TX/RX interfaces.
- TX and RX User Data Mapper
- This block maps the GT input or output data according to the AXI4-Stream protocol defined in the GT specification.
Additionally, the TX User Data Mapper multiplexes between normal AXI4-Stream data from HDMI TX MAC and the TX TMDS Pattern Generator when the Use 4th GT Channel as TX TMDS clock option is enabled. This connects to the 4th GT channel and provides the pattern to transmit the TMDS clock through the GT channel.
- Clock Generator
- This block also produces video clocks and differential and single-ended TX and RX Transition Minimized Differential Signaling (TMDS) CLK as per requirement of the