The HDMI GT Controller application requires a system clock and a minimum of three GT reference clock inputs for full duplex operation:
- System Clock
- HDMI TX from an external clock generator
- HDMI RX in CDR mode (normal operation)
- HDMI 1.4/2.0 RX NI-DRU mode and HDMI 2.1 FRL mode
The system clock should drive the
sb_aclk and the
axi4lite_aclk; the ports
should be connected to a 100 MHz clock. The system clock must be properly buffered
(using BUFG) before it can be used and connected.
Note the following constraints for the HDMI 1.4/2.0/2.1 reference clock:
- The HDMI TX and RX reference clock (Transition Minimized
Differential Signaling (TMDS) clocks) input frequency varies according to the input
video and both are maximized at 297 MHz. The corresponding input ports need to be
constrained at 297 MHz at the Vivado Project
top level XDC file for proper timing analysis and closure; that is,
create_clock -period 3.367 [get_ports <HDMI TX/RX REFCLK portname>].
- The HDMI 2.1 TX and RX reference clock (Transition Minimized Differential Signaling
(TMDS) clocks) input frequency varies according to the input video and both are
maximized at 297 MHz. The corresponding input ports need to be constrained at 400
MHz at the Vivado Project top level XDC file for proper timing analysis and closure;
create_clock -period 2.500 [get_ports <HDMI TX/RX REFCLK portname>].
- The NI-DRU reference clock frequency can be chosen from 3 values:
125.00 MHz, 200.00 MHz or 400.00 MHz. The NI-DRU reference clock frequency must be
constrained at the Vivado Project top level XDC
file at specified frequency; for example, 400 MHz:
create_clock -period 2.500 [get_ports <NI-DRU REFCCLK portname>]
The following figure illustrates the full reference clock requirement connections.
The HDMI TX reference clock comes from an external programmable clock generator capable of generating a range of frequencies from the minimum PLL reference clock (see HDMI TX Oversampled Reference Clock Requirements) to the maximum TMDS clock for supported video formats. For example, the HDMI GT Controller TX uses LCPLL and supports up to 4Kp60 at two pixels per clock. This means the programmable clock generator must be able to generate frequencies from 125 MHz to 297 MHz. For resolutions requiring lower TMDS clock than the minimum PLL reference clock, the HDMI GT Controller uses the oversampling technique (see the following section for details).
txrefclkport is accompanied by
tx_refclk_rdyport which indicates a lock condition. The
tx_refclk_rdyport has three requirements:
- It is connected to the external clock generator lock pin by
default or can be toggled through GPIO. It must be toggled (deasserted then
asserted) for every video format change. Alternatively, the TX Frequency Reset
bit (bit 3) of the Clock Detector Control register (0x200) can be set if the
tx_refclk_rdyport is active.
- It can only be asserted
when the clock at
txrefclk_p/nport is stable.
- At AXILITE CLK = 100 MHz, the
tx_refclk_rdyminimum hold time is 5 μs.
TX REFCLK frequency detection is sensitive only to the behavior of the
tx_refclk_rdy port, a change on which triggers the
clock detector to issue the TX frequency change event. The external clock generator is
set up for the desired TX clock frequency, which means that the HDMI GT Controller TX should get the requested frequency from the clock
generator. Because the assumption is that the HDMI GT Controller gets the correct clock, it only requires the LOCK event to
trigger the TX reconfiguration which is represented by the assertion of