TMDS Clock - 1.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID
PG334
Release Date
2022-04-21
Version
1.0 English

The TX TMDS clock output is implemented as differential output when the C_Use_GT_CH4_HDMI user parameters is set to false. If the parameter is set to true, the GT Channel 3 (4th channel) location must be properly constrained at the Vivado project top level XDC.

The RX TMDS and NI_DRU clock inputs are implemented as a GT reference clock input and therefore I/O standard constraints are not required.

IO Standard:

TX TMDS: set_property IOSTANDARD LVDS [get_ports HDMI_TX_CLK_P_OUT]
RX TMDS & NI-DRU: N/A

Sample Pin Assignments:

TX TMDS: set_property PACKAGE_PIN H21 [get_ports HDMI_TX_CLK_P_OUT] 
RX TMDS: set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] 
NI-DRU: set_property PACKAGE_PIN G8 [get_ports DRU_CLK_IN_clk_p]

Board design and connectivity should follow the HDMI standard recommendations with proper level shifting or TMDS driver use.