Using 4th GT Channel as the TX TMDS Clock Source - 1.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID
PG334
Release Date
2022-04-21
Version
1.0 English

HDMI 1.4 and 2.0 protocols use three GT channels in a Quad, leaving one unused. The 4th GT channel can be enabled and used as the TX TMDS clock source instead of being generated by DCM (MMCM or PLL). This is done by checking the HDMI GT Controller core customization screen option, Use 4th GT Channel as TX TMDS Clock. The gt_tx3 interface port must be connected to the GT Wizard’s TX3_GT_IP_Interface. Ensure that the Number of TX Lanes is four in the GT Wizard customization screen. For HDMI 2.1, the 4th GT channel is used as the TX TMDS clock source by default.

Figure 1. 4th GT Channel as TX TMDS Clock

When this option is enabled, the TX TMDS Clock ports, tx_tmds_clk_p/n output ports are disabled.

A pattern generator module is added in the HDMI GT Controller architecture to generate the specific pattern needed to generate the required TMDS clock frequency from the 4th GT channel. The pattern generator control register is located at offset 0x340 and is programmed based on the line rate to TMDS clock ratio. The pattern generator supports ratio of 10, 20, 30, 40, and 50. For example, in a typical HDMI 1.4 resolution such as 1080p60, the line rate per channel is 1.485 Gb/s and the TMDS clock is 148.5 MHz, thus giving a ratio of 10. For low line rate resolutions such as 480P60 which needs an oversampling technique (for example, x3) to be transmitted, the ratio is computed as actual line rate per channel (270 Mbs x 3) over TMDS clock (27 MHz), which gives a ratio of 30. For HDMI 2.0 resolution such as 4KP60, the line rate is 5.94 Gb/s and TMDS clock is 148.5 MHz, thus giving a ratio of 40.

In four channel FRL mode, the 4th GT channel is also used to transmit FRL data. Multiplexing between TMDS clock pattern and FRL data is automatically and internally handled by the HDMI PHY Controller and its software driver, depending on the operating mode. Additional device LUTs and flip-flops are consumed when the 4th GT Channel is enabled as the TX TMDS clock source. Be aware of these additional resources when enabling this option.

Table 1. Device Support
MAX FRL Data Rate 12 Gbps 4 Lanes 10 Gbps 4 Lanes 8 Gbps 4 Lanes 6 Gbps 4 Lanes 6 Gbps 3 Lanes 3 Gbps 3 Lanes TMDS
Device Family Speed Grade GT PLL
Versal
  • -1LP
  • -1LHP
  • -2LP
  • LCPLL
  • RPLL
Not Supported Supported
  • -1MP
  • -2HP
  • LCPLL
  • RPLL
Not Supported Supported
  • -2MP
  • -3HP
  • LCPLL
  • RPLL
Supported