General Design Guidelines - 1.0 English

The Audio Clock Recovery Unit IP can be used in two modes. The fixed mode can be used when the reference clock from the source is available at the receiver end. For HDMI solution, the receiver gets the same TMDS clock as source. As such, this mode can be used for HDMI solutions. In the fixed audio clock recovery mode, the audio sampling clock is recovered based on the values of N and CTS. This is good for HDMI as the TMDS clock is available at the receiver. The following figure shows the typical usage for HDMI:

Figure 1. Audio Clock Recovery - Fixed Mode

Following is the typical programming sequence in the fixed mode:

1. Set the mode register.
2. Program the registers 0x50 and 0x54 if operating in the user mode.
3. Program the register 0x70 to specify the divider value.
4. Start the ACR unit by writing 0x10 to 0x08 registers.

The following figure shows the clock connectivity in the HDMI example design:

Figure 2. Clock Connectivity in the HDMI Example Design

In the case of a DisplayPort, the receiver operates on a clock that is completely independent from the clock in the transmitter. During the audio clock recovery, you should ensure to match the jitter/ppm variation. This is because the Maud and Naud values are calculated based on the clocks in the transmitter. There is no guarantee that the clocks at the receiver will have similar properties. The loop control mode of the ACR is ideal for such a scenario. In this mode, the ACR unit continuously adjusts to match the incoming rate thereby ensuring a reliable audio clock recovery that avoids any overrun or under run of the audio buffer.

In the loop control based audio clock recovery mode, the ACR unit is adjusted based on the FIFO occupancy level. This is helpful in adjusting the jitter/PPM when the reference clock at the receiver end is independent of the transmitter. This is suited for the DisplayPort. In this mode, the ACR output varies based on the FIFO occupancy level, which in turn affects the output of an external chip thereby adjusting the jitter/PPM. For example, for a 48 KHz audio, the output clock could vary continuously between 47 KHz and 49 KHz in order to maintain the FIFO level.

Figure 3. Audio Clock Recovery - Loop Control Mode

Following is the typical programming sequence in the loop control mode:

1. Set the mode register.
2. Program the registers 0x50 and 0x54 if operating in the user mode.
3. Program the register 0x70 to specify the divider value.
4. Program the FIFO set point register 0x30.
5. Program the registers 0x34 and 0x38 to specify the delta limit and size.
6. Program the registers 0x3C and 0x40 to specify the sample pulse control and FIFO average control.
7. Start the ACR unit by writing 0x1 to 0x08 registers.

The following figure shows the clock connectivity in the DisplayPort example design:

Figure 4. Clock Connectivity in the DisplayPort Example Design