Core Overview - 1.0 English

Versal ACAP Soft ECC Proxy v1.0 LogiCORE IP Product Guide (PG337)

Document ID
Release Date
1.0 English

This product guide describes features of the Xilinx® Soft ECC Proxy LogiCORE IP and the functionality of the various registers in the design. In addition, the core interface and its customization options are defined in the following sections.

Figure 1. Soft ECC Proxy IP Basic Block Diagram

Soft ECC Proxy IP consists of AXI4 memory mapped master (AXI4-MM Master) and slave (AXI4-MM Slave) interfaces. The ECC bits are calculated for every byte of write data from the slave. The calculated ECC bits puts on to master interface along with its data, which then reads from the master interface. The ECC decoding is done on the read data from master interface and generate interrupts (single/double bit error) for every byte of read data. The status of the interrupts can be accessed through the Interrupt Status Register. The Common ECC interrupt pin at the output represents the ECC error occurred. The register space inside the IP is accessed through the AXI4-Lite interface. In case of an interrupt, the type of error (single-bit or double-bit) can be read from the Interrupt Type Register. And the corresponding byte or bit is set in the Interrupt Status Register.