- Support for AXI4 and AXI4-Lite
- Configurable data width from 8 to 512 (the data width must be power of 2).
- ECC calculation for every data byte
- Single-bit error detection and correction. When there is a single-bit error, the bit is corrected along with the correction being notified.
- Double-bit error detection for every data byte
- Hard and soft reset
- Configurable outstanding transaction support of up to 64 bits for the read channel
- Doubled data width value when ECC is applied
- Support for Hamming and Hsiao ECC modes
- Error injection (single-bit and double-bit error)
- Slave error response in case of error detection
- Error start address capturing in registers
- Error count for single-bit and double-bit errors