IP Facts - 1.0 English

Versal ACAP Soft ECC Proxy v1.0 LogiCORE IP Product Guide (PG337)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal™ ACAPs
Supported User Interfaces AXI4, AXI4-Lite
Resources Performance and Resource Use web page
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File Not Provided
Simulation Model Not Provided
Supported S/W Driver N/A
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Provided by Xilinx at the Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.