The demonstration test bench is a straightforward Verilog-HDL file that can be used to exercise the example design and the core itself. The test bench consists of the following:
- Clock generators
- Data generator module
- Data verifier module
- Module to control data generator and verifier
The demonstration test bench in a core with an AXI interface performs the following tasks:
- Input clock signals are generated.
- A reset is applied to the example design.
- Pseudorandom data is generated and given as input to AXI interface input signals. Each channel is independently checked for valid-ready handshake protocol.
- AXI output signals on the read side are combined and cross checked with the pseudorandom generator data.
- For the AXI memory mapped interface, five instances of the data generator, data verifier, and protocol controller are used.