Test Bench Functionality - 1.0 English

Versal ACAP Soft ECC Proxy v1.0 LogiCORE IP Product Guide (PG337)

Document ID
Release Date
1.0 English

The demonstration test bench is a straightforward Verilog-HDL file that can be used to exercise the example design and the core itself. The test bench consists of the following:

• Clock Generators

• Data generator module

• Data verifier module

• Module to control data generator and verifier

The demonstration test bench in a core with an AXI interface performs the following tasks:

• Input clock signals are generated.

• A reset is applied to the example design.

• Pseudo random data is generated and given as input to AXI Interface input signals. Each channel is independently checked for Valid-Ready handshake protocol.

• AXI output signals on read side are combined and cross checked with the pseudo random generator data.

• For AXI memory mapped interface five instances of data generator, data verifier and protocol controller are used.