Configuring Clock Wizard - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Version
4.1 English
An instance of the Xilinx clock wizard IP can implement the above circuit. The following example is provided to illustrate how the user can implement such a design.  In this example, the frequency of s_axi_aclk is set to 100 MHz and m_axi_dpu_aclk is set to 325 MHz. Therefore, the frequency of the dpu_2x_clk should be set to 650 MHz accordingly. The recommended configuration of the Clocking Options tab is shown in the following figure.
Note: The primitive parameter radio button must be set to Auto.
Figure 1. Recommended Clock Wizard Clocking Options

In addition, Matched Routing must be selected for m_axi_dpu_aclk and dpu_2x_clk in the Output Clocks tab of the Clock Wizard IP. The Matched Routing option ensures that the skew between two or more output clocks from the Clock Wizard IP (in this case, the output of the two BUFGCE_DIV instances) is minimized. The related configuration is shown in the following figure.

Figure 2. Matched Routing in Clock Wizard
Note: When populating the Output Clocks tab, populate the clocks from the highest frequency to the lowest.  This ensures that the architecture implemented leverages the BUFGCE_DIV. The following figure shows the correct sequence. The settings in figure (a) achieved the dedicated clock design in the Summary page while the figure (b) did not. For instance, we find that the frequency ordering used in Figure 18(a) generates two BUFGCE_DIV buffers, while the incorrect ordering used in Figure 18(b) will produce an instantiation that leverages two discrete outputs from the PLL or MMCM, with the result that the output skew is non-ideal. For more details, refer to the Clocking Wizard LogiCORE IP Product Guide (PG065).
Figure 2. Comparison of clkout Frequency Sequence