Connecting the DPUCZDX8G to the Processing System in the Zynq UltraScale+ MPSoC - 4.0 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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The DPUCZDX8G IP contains only one slave interface. The number of DPUCZDX8G cores depends on the parameter DPU_NUM, which is configured through the Number of DPU Cores option in the wizard. Each DPUCZDX8G core has three master interfaces, one for instruction fetch, and the other two for data access.

The DPUCZDX8G IP can be connected to the processing system (PS) with an AXI Interconnection IP as long as the DPUCZDX8G can correctly access the DDR memory space. Generally, when data is transferred through an Interconnect IP, the data transaction delay will increase. The delay incurred by the Interconnect will reduce the DPUCZDX8G performance. Therefore, Xilinx recommends that each master interface in the DPUCZDX8G is connected to the PS through a direct connection rather than through an AXI Interconnect IP when there are sufficient AXI slave ports available on the PS.

When the AXI slave ports of the PS are insufficient for the DPUCZDX8G, an AXI interconnect for connection is unavoidable. The two AXI master ports for data fetching are high bandwidth ports and the AXI master port for instruction fetching is a low bandwidth port. Typically, it is recommended that all the master ports for instruction fetching connect to the S_AXI_LPD of PS through one interconnect. The rest of the master ports for data fetching should be directly connected to the PS as much as possible. Xilinx recommends that the master ports of the DPUCZDX8G core with higher priority (smaller number, like DPU0) be directly connected to the slave ports of the PS with higher priority (smaller number, like S_AXI_HP0_FPD).

For example, if there are three DPUCZDX8G cores and one SFM core, there will be seven master ports, and four slave ports: S_AXI_HP1~3 and S_AXI_HPC0. A possible connection setup would be:

  • DPU0_DATA0 to HP1
  • DPU0_DATA1 to HP2
  • DPU1_DATA0 and DPU1_DATA1 to HP3
  • DPU2_DATA0, DPU2_DATA1, and SFM to HPC0

It is recommended that the slave port of DPUCZDX8G be connected to M_AXI_HPM0_LPD of the PS.

A reference connection between the DPUCZDX8G and PS in theZynq UltraScale+ MPSoC is shown here. The number of DPUCZDX8G core is set to three, and the Softmax function is enabled.

Figure 1. DPUCZDX8G and PS Connections for Zynq UltraScale+ MPSoC