Data Controller Clock - 4.0 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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4.0 English

The primary function of the data controller module is to schedule the data flow in the DPUCZDX8G IP. The data controller module is clocked from m_axi_dpu_aclk. Data transfer between the DPUCZDX8G and external memory is clocked from the data controller clock domain, thus, m_axi_dpu_aclk serves as a clock source for both the data controller and the AXI_MM master interface. m_axi_dpu_aclk should be connected to the AXI_MM master clock.