Features - 4.0 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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4.0 English
  • Supports one AXI slave interface for accessing configuration and status registers.
  • Supports one AXI master interface for instruction fetch.
  • Supports individual configuration of each channel.
  • IP is available in multiple variants, scaling both in terms of logic resource utilization and parallelism.  Configurations include: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096, where the nomenclature indicates the total number of MACs per DPU clock cycle.
  • Software and IP core support for up to a maximum of four homogeneous DPU instances in a single Xilinx SoC

The following list highlights key supported operators for the DPUCZDX8G :

  • Supports both Convolution and transposed convolution
  • Depthwise convolution and depthwise transposed convolution
  • Max pooling
  • Average pooling
  • ReLU, ReLU6, Leaky ReLU, Hard Sigmoid, and Hard Swish
  • Elementwise-sum and Elementwise-multiply
  • Dilation
  • Reorg
  • Fully connected layer
  • Softmax
  • Concat, Batch Normalization