Interrupts - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Version
4.1 English

A high state on reg_dpu0_start signals the start of a DPUCZDX8G task for DPUCZDX8G core0. At the end of the task, the DPUCZDX8G generates an interrupt to signal the completion of a task, and bit0 in reg_dpu_isr is set to 1. The position of the active bit in the reg_dpu_isr depends on the number of DPUCZDX8G cores. For example, when DPUCZDX8G core1 finishes a task while DPUCZDX8G core0 is still processing, reg_dpu_isr would contain 2’b10.

The DPU IP may be configured to instantiate 1-4 cores (see DPU Configuration).  The IP wrapper for the configured DPU will have up to four dpux_interrupt signals, corresponding to the number of cores. These signals must be routed through a concat block, and then be connected to the PS as illustrated in the following image.

Figure 1. Interrupt Concatenation for Multiple DPU Cores
Note:
  1. irq7~irq0 corresponds to pl_ps_irq0[7:0].
  2. irq15~irq8 corresponds to pl_ps_irq1[7:0].