The m_axi_dpu_aclk (1x) and
dpu_2x_clk clock must be
synchronous and edge-aligned. While there are various techniques available to achieve this,
the recommended clock topology is illustrated in the figure below:
As shown, MMCM and two BUFGCE_DIV blocks are instantiated to generate the 1x
and 2x clocks. The frequency of
clk_in1 is arbitrary and the
frequency of MMCMCLKOUT should selected to be equal to the target frequency of
dpu_clk_2x (BUFGCE_DIV_CLK2_INST BUFGCE_DIVIDE =1).
BUFGCE_DIV_CLK1_INST in turn is configured to divide the MMCM output clock frequency by two
(BUFCE_DIVIDE=2). The resulting two output clocks are synchronous and phase aligned.
Dedicated routing from the MMCM to BUFGCE_DIV instances ensures that skew between the two
clocks is minimized.