Register Space - 4.1 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Version
4.1 English

The DPUCZDX8G IP implements registers in programmable logic. The following tables show the DPUCZDX8G IP registers. These registers are accessible from the APU through the S_AXI interface.