The AXI Memory Init IP core can be inserted along any AXI pathway that accesses the memory device to be initialized. The example design shown in the following figures contains two DDR4 memory instances (4 GB each) accessed by a DMA master through a SmartConnect switch.
In the figure, an instance of the AXI Memory Init is inserted immediately before each DDR4 instance. Following reset, both AXI Memory Init cores begin initializing their respective memories in parallel.
Notice how the init_complete signals of the
two AXI Memory Init instances are daisy-chained to provide a
composite completion signal to an interrupt request input. The init_complete_in of the first instance can be left unconnected (default tie-off
High), tied High or driven by another initialization completion signal, such as a calibration
completion output from a memory controller. In the figure, init_complete_in is driven by the same signal that drives the aresetn input of the IP, for convenience, as it remains High during
operation.
Both instances of AXI Memory Init are configured the same manner, as shown in the following figure. Notice that the base address of 0 works for both memories, because the AXI Memory Init instances are placed immediately before the memories.
In the following figure, one instance of AXI Memory Init is inserted before the SmartConnect switch that accesses both memories, plus other slave devices. The memories are mapped to adjacent address ranges in the system address map. Following reset, the AXI Memory Init core sweeps across their combined address space, initializing both memories.
The figure shows the configuration of the AXI Memory Init core. Its base address must be set to the base address of the first memory. Its Address Range parameter is set to 33, indicating that it initializes a total memory space of 8 GB.
