Generating the Core - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
Document ID
PG343
Release Date
2023-11-10
Version
1.0 English
To generate a core using the default values in the AMD Vivado™ IDE, follow these steps:
  1. Start the Vivado IP catalog.
  2. Select File > Project > New.
  3. Enter a project name and location, click Next. This example uses project_name.xpr and project_dir.
  4. In the New Project wizard pages, do not add sources, existing IP, or constraints.
  5. From the Part tab (below), select these filter options:
    • Family: AMD Versal™
    • Device: xcvc1902
    • Package: vsvd1760
    • Speed Grade: -2MP
    Note: If an unsupported silicon device is selected, the core is grayed out (unavailable) in the list of cores.
  6. Select xcvc1902-vsvd1760-2MP-e-S from the list.
  7. In the final project summary page, click OK.
  8. In the Vivado IP catalog, expand Standard Bus Interfaces > PCI Express, and double-click Versal Adaptive SoC Integrated Block for PCIe to display the Customize IP dialog box.
  9. In the Component Name field, enter a name for the core.
    Note: <component_name> is used in this example.
  10. From the Device/Port Type drop-down menu, select the appropriate device/port type of the core (Endpoint or Root Port).
    Tip: The PCIe reset pin for PL PCIe designs can be connected to any compatible single ended PL I/O pin location. If your board is compatible for either CPM4 or PL PCIe usage, you can use the CPM4 pin MIO38 to route the sys_rst_n. When this is done, the PL PCIe can use the reset as routed to the PL.
    Before opening the example design, set the following Tcl property to use the reset on the MIO38 pin:
    set_property CONFIG.insert_cips {true} [get_ips pcie_versal_0]
  11. Click OK to generate the core using the default parameters.