|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive SoC |
| Supported User Interfaces |
AXI4-Stream
|
| Resources |
Performance and Resource Use web
page
|
| Provided with Core
|
| Design Files |
Verilog |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Constraints file (XDC) |
| Simulation Model |
Verilog |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 73083
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|