- Designed to the PCI Express Base
Specification 4.0 and Errata updates
-
PCI Express Endpoint, Switch Port Upstream, Switch Port
Downstream, Legacy Endpoint, and Root Port Modes
- Gen1, Gen2, Gen3, and Gen4 speeds upto x16 link width is supported with
some limitation in Gen4. For more information, see Table 1.
-
AXI4-Stream interface to customer
logic
- Configurable 64-bit/128-bit/256-bit/512-bit data path widths
- Four Independent Initiator/Target, Request/Completion streams
- Parity protection on internal logic data paths and data interfaces
- Advanced Error Reporting (AER) and End-to-End CRC (ECRC)
- UltraRAM used for Transaction Layer Packet buffering
- 32 KB – Replay Buffer
- Configurable 16 KB, or 32 KB – Received Posted Transaction FIFO
- Configurable 32 KB, or 64 KB – Received Completion Transaction
FIFO
- UltraRAM ECC protection enabled
- One Virtual Channel, eight Traffic Classes
- Supports multiple functions and single-root I/O virtualization (SR-IOV)
- Up to four Physical Functions
- Up to 252 Virtual Functions
- Built-in lane reversal and receiver lane to lane de-skew
- 3 x 64-bit, or 6 x 32-bit Base Address Registers (BARs) that are fully
configurable
- Expansion ROM BAR supported
- All Interrupt types are supported
- INTx
- 32 multi-vector MSI capability
- MSI-X capability with up to 2048 vectors with optional to use,
built-in vector tables
- Built-in Initiator Read Request/Completion Tag Manager
- Up to 256 or 768 outstanding Initiator Read Request Transactions
supported
- Advanced Peripheral Bus (APB3) interface is available to perform DRP
operations.
- Features that enable high performance applications
-
AXI4-Stream TLP Straddle on
Requester Completion Interface
- Up to 1024 RX Completion Header Credits, and 64 KB RX Completion
Payload Space (10b tag enabled)
- Relaxed Transaction Ordering in the Receive Data Path
- Address Translation Services (ATS) Messaging
- Atomic Operation Transactions Support
- Transaction Tag Scaling as Completer
- Flow Control Scaling
- Low latency PIPE interface operation 32b at 500 MHz
- Several ease of use and configurability features are supported
- BAR and ID based filtering of Received Transactions
- Optional ASPM support for endpoint port types only; ASPM is not
supported for other port types
- Configuration Extend Interface
-
AXI4-Stream Interfaces Address
Align Mode
- Debug and Diagnostics Interface
- Self Train over loopback on PCI Express link
-
PCIe extended capabilities (optional capabilities)
- Device serial number capability
- Virtual channel capability
- ARI capability
- SR-IOV extended capability structure
- Configuration space extended capabilities
- Address translation services (ATS)
- Page request interface (PRI)
- PASID
- Feature DLLP
- CCIX transport DVSEC via configuration space extension
- Data link layer feature extended capability
- Physical ayer 16.0 GT/s extended capability
- ACS extended capability and ACS error logging/reporting
- Lane margining at receiver extended capability