RX Data Signals - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID: PG343
Release Date: 2023-11-10
Version: 1.0 English

Table 1. RX Data Signals
Name	I/O	Width	Description
phy_rxdata[63:0]	I	64	PIPE data output from receiver. Bits[63:32] are used for Gen4 only and must be ignored in Gen1, Gen2, and Gen3. Bits[31:16] are used for Gen3 only and must be ignored in Gen1 and Gen2. Per lane.
phy_rxdatak[1:0]	I	2	Indicates whether RXDATA is control or data. Gen1 and Gen2 only. Per-lane. 0b: Data 1b: Control
phy_rxdata_valid	I	1	This signal allows the PHY to instruct the MAC to ignore RXDATA for one pclk cycle. When High, this indicates that RXDATA should be used. When Low, this indicates the RXDATA should be ignored for one pclk cycle. Gen3 and Gen4 only. Per lane.
phy_rxstart_block[1:0]	I	2	This signal allows the PHY to tell the MAC the starting byte for a 128b block. 00b: Data with no start 01b: A block starts at lower 32 bits 10b: A block starts at upper 32 bits, inactive when operating at Gen3 speed 11b: Lower 32 bits has valid data and upper 32 bits are invalid, inactive when operating at Gen3 speed. Gen3 and Gen4 only per lane.
phy_rxsync_header[1:0]	I	2	Provides the sync header for the MAC to use the next 128b block. The MAC reads this value when the RXSYNC_BLOCK is asserted. Gen3 and Gen4 only. Per lane.