Target logic is responsible for capturing single Dword memory write (MWr) and memory read (MRd) transaction layer packets (TLPs) presented on the interface. MWr and MRd TLPs are sent to the endpoint through Programmed Input/Output (PIO) transactions, and are used to monitor and control the DMA hardware. The function of the target logic is to update the status and control registers during MWr transactions and return Completions with Data for all incoming MRd transactions. All incoming MWr packets are 32-bit and contain a one Dword (32-bits) payload. Incoming MRd packets should only request 1 Dword of data at a time resulting in Completions with Data of a single Dword.