AXI Bridge Subsystem Limitations - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English
  1. For this subsystem, the bridge master and bridge slave cannot achieve more than 128 Gb/s.
  2. Bridge is compliant with all MPS and MRRS settings; however, all the traffic initiated from the Bridge is limited to 256 bytes (max).
  3. AXI address width is limited to 48 bits.