AXI4 Memory Mapped Write Response Interface Signals - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2023-11-10
Version
2.0 English
Table 1. AXI4 Memory Mapped Write Response Interface Signals
Signal Name Direction Description
m_axi_bvalid I Master write response valid.
m_axi_bresp[1:0] I Master write response.

m_axi_bid

[ID_WIDTH-1:0]

 I Master response ID.
m_axi_bready O Master response ready.