AXI4-Stream C2H Write Completion Ports

AXI4-Stream C2H Write Completion Ports - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2023-11-10

Version

2.0 English

Table 1. AXI-ST C2H Write Completion Port Descriptions
Port Name	I/O	Description
axis_c2h_dmawr_cmp	O	This signal is asserted when the last data payload write request of the packet gets the write completion. It is one pulse per packet.